The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor.
Modern electronics achieve high levels of functionality in small and compact form factors by integrating multiple functions onto a single chip. A common fabrication process that allows high levels of integration at a relatively low cost is complementary metal-oxide-semiconductor (CMOS). CMOS processes build a combination of p-channel and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement logic gates and other types of digital circuits, as well as analog circuits. A field-effect transistor includes a gate electrode and source/drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel within the substrate between the source/drain regions.
Middle-of-line (MOL) processing includes the formation of gate contacts and source/drain contacts. A tie-off structure may be formed during middle-of-line MOL processing may be used to couple or “tie-off” a drain or source of a field-effect transistor to a dummy gate. The tie-off structure includes metallization formed in a MOL dielectric layer that couples the gate contact with one of the source/drain contacts of the field-effect transistor. Another way to couple the dummy gate to ground or power is to terminate one side of the active area at which the dummy gate is located, which prevents the dummy gate from forming a drain contact. This is known as a “diffusion break approach”. The diffusion break approach may use two dummy gates, one dummy gate on each side of the broken active area.
Improved structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor are needed.